FIG. 1 shows a block diagram of a generic wireless transceiver, in which a processing circuit 10, such as, for example, a digital signal processor (DSP), supplies a baseband (EB) transmitting signal TXBB. The above baseband transmitting signal TXBB is converted by a transmitter circuit 20 into a radio frequency (RF) transmitting signal TXRF. For instance, typically this transmitter circuit 20 comprises a modulator, such as, for example, a mixer or an analog multiplier, which modulates the signal TXBB with a high-frequency carrier signal LO. In addition, this transmitter circuit may also comprise filters, amplifiers, etc. Finally, the transmitting signal TXRF is sent to at least one antenna 30.
In a complementary way, an RF receiving signal RXRF received via the antenna 30 is converted via a receiver circuit 40 into a baseband receiving signal RXBB. For instance, typically this receiver circuit 40 comprises a demodulator, such as, for example, a mixer, which demodulates the signal RXRF using the carrier frequency LO. Also the receiver circuit may comprise filters, amplifiers, etc. For instance, the carrier signal LO may be supplied by an oscillator or synthesizer 50.
A particular architecture of the receiver 40 is the architecture of a so-called “low-intermediate frequency (low-IF)” type. Basically, in a low-IF receiver, the RF signal RXRF received is demodulated at a lower, non-zero, frequency, the so-called “intermediate frequency”, which typically may range from hundreds of kilohertz (kHz) to some Megahertz (MHz).
Receivers with a low-IF architecture are commonly used in transceiver systems on account of their relatively low complexity and their robustness. The main characteristic of this architecture may comprise the fact that the RF signal RXRF received is converted by means of a system of a heterodyne type to a significantly lower frequency, hereinafter designated by fIF. In particular, the heterodyne system is implemented through a mixer that carries out multiplication of the radio frequency signal by an ideally pure tone (LO) with frequency fLO, appropriately generated by the synthesizer 50 in such a way that:fIF=fRF−fLO.   (1)
The high-frequency components generated by the multiplication can be subsequently filtered along the receiving chain. The choice of the frequency fIF has a considerable effect on the design of the analog system in so far as, if it is sufficiently high, it enables reduction of the problems of flicker noise and DC offsets generated by the chain of receiver circuits. On the other hand, an excessive increase of the frequency fIF may lead to an increase of the power dissipation of the analog-to-digital converter (ADC) and also of the digital signal processor (DSP) in so far as it requires a higher operational frequency.
Low-IF receivers normally use in-phase and quadrature signals (i.e., of a complex-envelope type) both to facilitate demodulation thereof and to solve the problem of image rejection. The in-phase and quadrature signals are periodic waveforms that have a phase difference equal to one quarter of their period, namely, 90°.
Consequently, as shown in FIG. 2, the low-IF receiver circuit 40 receives at input the radio frequency receiving signal RXRF. In the example considered, this signal is amplified via an amplifier 402, such as, for example, a low-noise amplifier (LNA).
In particular, in the case where the receiver 40 operates with signals I and Q that are in quadrature with respect to one another, the amplified signal, i.e., the signal at output from the amplifier 402, is sent to two branches: a first branch for the in-phase component I and a second branch for the quadrature component Q. In this case, each branch comprises a demodulator 404, such as, for example, a mixer, which carries out multiplication of the radio frequency signal by respective signals LOI and LOQ, and a filter 406, which, by filtering the high-frequency components, yields the evolution in time of the respective component IRX and QRX. To interface those signals with the processing circuit 10, respective analog-to-digital (A/D) converters 408 may be provided.
Consequently, reception of a complex signal calls for generation, upstream, of the in-phase signal LOI and the quadrature signal LOQ, namely, signals that have a phase shift of 90° with respect to one another. Generation of the tones LOI and LOQ with controlled phase shift may call for an accurate design of the circuit 50 that may limit as far as possible the inevitable cumulative phase errors.
The techniques normally employed envision use of synthesizers based upon PLLs containing an oscillator, such as, for example, a voltage-controlled oscillator (VCO) 502, and polyphase filters or frequency dividers 504. The latter approach, however, envisions generation of a tone by the synthesizer, the frequency of which should be at least twice the desired one.
Working against this disadvantage, the approach based upon dividers may enable generation of in-phase and quadrature signals over a wide range of frequencies, unlike the approach based upon polyphase filters, which are intrinsically narrowband filters. The precision on the amplitude and phase of the in-phase and quadrature signals I and Q may be important in RF communication systems that adopt the low-IF architecture, since it affects the levels of performance of the receiver in terms of bit-error rate (BER). The low-IF architecture presents in fact an image signal that may be very close to the channel of interest and that hence may require use of two in-phase and quadrature signals for implementing rejection of the image signal.
A typical problem of the low-IF receiver may be the so-called “image response or rejection.” With reference to FIG. 3a, the problem includes that a generic heterodyne system produces a frequency conversion both of the desired channel CHN, in this case at a frequency fCHN=fLO+fIF, and of its image IMG positioned at fIMG=fLO−fIF, which at this point cannot be rejected with a classic real analog filter, such as, for example the filter 406. This is in so far as both of the channels are brought to the frequency fIF, since the components CHN and IMG are superimposed during demodulation in the demodulators 404 (see FIG. 3b).
Image rejection, as well as selection of the channel CHN, may in any case be made by complex-filtering techniques, which can be implemented either in an analog or in a digital way and operate on the complex (in-phase and quadrature) signal received by selecting the desired channel CHN from the image IMG and from other possible out-of-band interfering signals. The effectiveness of the complex filter in rejection of the image IMG is, however, markedly affected by the phase and amplitude mismatch or errors that accumulate on the in-phase and quadrature signals at input. Here, the phase mismatch is defined as the deviation with respect to the 90° phase shift expected between the signals I and Q, and the amplitude mismatch is defined as the lack of amplitude correspondence between the signals I and Q.
FIG. 4 shows a typical relation for image rejection (IR) with respect to the phase mismatch, or “Phase Imbalance”, as appears on the horizontal axis, and the amplitude mismatch, or “Amplitude Imbalance”, as appears on the vertical axis. The errors of the in-phase and quadrature signals I and Q are correlated to the image-rejection (IR) ratio.
The image-rejection ratio is described, for example, in the paper by Q. Gu, “RF System Design of Transceivers for Wireless Communications,” New Work, USA, Springer, 2005. The relation that expresses the image rejection IR with respect to the phase mismatch φ and the amplitude mismatch δ may be expressed via the following equation:
                              IR          =                      10            ⁢                                                  ⁢            log            ⁢                                          1                +                                  2                  ⁢                                      (                                          1                      +                      δ                                        )                                    ⁢                  cos                  ⁢                                                                          ⁢                  φ                                +                                                      (                                          1                      +                      δ                                        )                                    2                                                            1                -                                  2                  ⁢                                      (                                          1                      +                      δ                                        )                                    ⁢                  cos                  ⁢                                                                          ⁢                  φ                                +                                                      (                                          1                      +                      δ                                        )                                    2                                                                    ;                            (        2        )            where δ is the amplitude error (expressed in decibels) and φ is the phase error with respect to the ideal 90° phase shift between the two signals I and Q.
From Eq. (2) it emerges that rejection of the image is increased when the amplitude error (δ) and quadrature error (φ) are decreased. Specifically, a phase error (φ) of 0.2° makes it possible to obtain a rejection IR of 50 dB without requiring excessively stringent specifications on the amplitude error (δ<0.03 dB). Consequently, normal techniques for correction of the errors are introduced in such a way as to maximize the image rejection available according to the specifications of the system and to the effective selectivity of the complex filter.
For instance, the technique described in Li Yu, W. Martin Snelgrove, “A Novel Adaptive Mismatch Cancellation System for Quadrature IF Radio Receivers,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 6, JUNE 1999, is used because it operates digitally on the complex signal received, producing a simultaneous correction of amplitude and phase mismatch prior to complex filtering.
Alternatively, the technique described in Oscar Steila, “Automatic In-phase Quadrature Balancing AIQB”, October 2006 (Rev C: Jul. 10, 2012) may be used, where a mismatch correction is made by correlating appropriately different harmonic contributions of the signal received. This approach calls, however, for an operation of Fast Fourier Transform (FFT), which is typically more burdensome from the computational standpoint. However, the increasing demand for low-consumption systems may clash with the need of producing high-performance ADC circuits, which in general prove particularly burdensome from the consumption standpoint and frequently force the digital circuitry to operate at higher sampling frequencies, thus weighing even more heavily on the power budget.
Optimization of the circuits and appropriate distribution of the functions linked to selection of the channel CHN within the low-IF architecture may, however, contribute significantly to the reduction of the overall consumption of the system, reducing in particular the performance required of the ADC and the digital circuitry. In this sense, the architecture in FIG. 5 contemplates the presence of a complex filter 412 of an analog type upstream of the A/D conversion. The complex filter 412 is ideally able to select the desired channel CHN from any other interfering channel (including the image IMG), intrinsically limiting the band requirement and the resolution of the ADC and hence also the consumption of the processing unit 10. Elimination of the image channel IMG may enable for some specific modulation formats demodulation of the channel received without necessarily having a complex signal, and consequently it is possible to eliminate also one of the two A/D converters 408.
Working against these advantages may be the problem of correction of the phase and amplitude errors at input to the complex filter 412. Due to the presence of the filter and of an A/D converter with limited performance, it is not possible to use the techniques disclosed by Yu et al. and Steila.
Working an these example of FIG. 5, it is disclosed to correct possible phase errors by acting appropriately at the level of the signal LO, for example, on the frequency dividers (circuit 504), and on the amplitude error at the baseband level, for example, by adding a respective amplifier with configurable amplification coefficient 410 between the filter 406 and the filter 412. In general, the simplest generators of in-phase and quadrature signals are systems that exploit open-loop approaches, such as, for example, polyphase passive filters or frequency dividers in the master-slave configuration, as in FIGS. 6a and 6b. 
For instance, the technique described in S. Kulkarni, D. Zhao, and P. Reynaert, “Design of an optimal layout polyphase filter for millimeter-wave quadrature LO generation,” in IEEE Trans. Circuits Syst. II, vol. 60, No. 4, pp. 202-206, April 2013, is a technique that uses the polyphase filters for supplying a circuit for generation of the carrier signals LOI and LOQ. In particular, with an RC network like the one illustrated in FIG. 6a, it is possible to generate at output signals phase-shifted with respect to an input signal VIN.
More specifically, the circuit comprises four resistors R1, R2, R3 and R4, four capacitors C1, C2, C3, and C4, and four outputs O1, O2, O3, and O4. The input signal VIN is supplied to two nodes PA and PB that are common to two of the four branches. The four outputs O1, O2, O3, and O4 supply signals 90° phase-shifted with respect to one another, in particular, signals phase-shifted by 0°, 90°, 180°, and 270° with respect to the input signal VIN.
The resistors R1, R2, R3 and R4 and the capacitors C1, C2, C3, C4 are connected alternately in a loop configuration, and the input nodes PA and PB and the output nodes O1, O2, O3, and O4 are connected alternately to the respective node between the resistor and the capacitor in sequence. Alternatively, it is possible to use the technique described in R. Nonis, E. Palumbo, P. Palestri, and L. Selmi, “A design methodology for MOS current-mode logic frequency dividers,” in IEEE Trans. Circuits Syst. I, vol. 54, No. 2, pp. 245-254, February 2007. In particular, in the technique described, an integer divider is used that divides the frequency of the input signal by an integer that is a multiple of two. For instance, a divider may be obtained with a connection of two or more flip-flops in cascade. By connecting a plurality of flip-flops in cascade at each output, a signal having a frequency that is half the previous one is obtained.
With reference to FIG. 6b, the signal fIN is sent at input to two flip-flops FF1 and FF2 connected in master-slave configuration. The signal fIN is connected to the clock inputs CK and CK of the two flip-flops. The first flip-flop FF1 has a data input D and an output Q, whereas the second flip-flop FF2 has a data input D and an output Q that is in quadrature (i.e., 90° phase-shifted) with respect to the output Q. The two outputs supply the desired in-phase and quadrature signals, for example, the first flip-flop FF1 returns the signal fOUT_Q and the second flip-flop FF2 returns the signal fOUT_I. The output Q of the first flip-flop FF1 is connected to the input D of the second flip-flop FF2, whereas the output Q of the second flip-flop FF2 is fed back to the input D of the first flip-flop FF1.
The output signals may have a frequency halved with respect to the input signal fIN and may be 90° phase-shifted with respect to one another. However, generators of in-phase and quadrature signals based upon polyphase filters are intrinsically narrow-band generators, unless higher-order filters are used, which would lead both to high losses and to a high energy consumption. Instead, a frequency divider in master-slave configuration is able to supply in-phase and quadrature signals over a wide range of frequencies. However, both of the approaches described above may not guarantee the precision required for the phase errors in the in-phase and quadrature signals I/Q. Moreover, other known systems are for obtaining in-phase and quadrature signals that are accurate with respect to process, voltage, and temperature (PVT) variations and that exploit feedback control systems that detect and correct the phase errors appropriately.
A few examples of the systems are described are: S. F. Gilling, “Circuit for generating signals in phase quadrature and associated method therefor”, U.S. Pat. No. 5,375,258 to Gillig, Dec. 1994; A. Y. Valero-Lopez, S. T. Moon, and E. Sanchez-Sinencio, “Self-calibrated quadrature generator for WLAN multistandard frequency synthesizer,” in IEEE J. Solid State Circuits, vol. 41, No. 5, pp. 1031-1041, May 2006; and—C. M. Ippolito, A. Italia, and G. Palmisano, “A CMOS auto-calibrated I/Q generator for Sub-GHz ultra low-power transceivers,” in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., pp. 319-322, June 2011.
For instance, the approach proposed in the '258 patent exploits a control loop that regulates the duty cycle of the carrier signal I to minimize the mean phase error at output from a divide-by-two circuit. Even though the above techniques may be simple and effective, they are, however, unable to guarantee in all cases the required precision.
For instance, in the technique referred to by Valero-Lopez, the phase error at output from a polyphase filter is compensated for by a multi-loop system, which exploits phase-shifters active for minimizing the phase error at output. The system supplies four output signals phase-shifted with respect to one another by 0°, 90°, 180°, and 270°, respectively. Phase control is provided by tuning three of the four output phases, for example, the outputs at 90°, 180°, and 270°, with respect to input phase, which is assumed as reference. This technique ensures a high precision in generation of in-phase and quadrature signals, but the control loops are markedly dependent, and require a sequential calibration technique for guaranteeing a stable operation of the entire system.
The above problem is overcome partially by the approach proposed by Ippolito, Italia, and Palmisano, which carries out the phase correction by circuits with resistive loads (source-coupled-logic—SCL—dividers and limiting amplifiers). To increase the precision, phase control is obtained by tuning both the time delay between the in-phase and quadrature signals I and Q and their duty cycles. Control of timing is carried out at the level of the divider by changing the load resistances of the divider and regulating the rising and falling edges of the in-phase and quadrature signals I and Q, whereas control of the duty cycle is carried out in the limiting amplifier by modifying the load resistances associated thereto. However, the control loops implemented in the latter technique described have a mutual second-order dependence, which may lead to a not altogether stable operation.